FrontPanel SDK Examples

These pages include a number of resources to help make you more productive with our products. Please refer to the following resources if you need a hand.

HDL Framework (USB 3.0)

This section contains template definitions of the top-level module for FrontPanel-enabled USB 3.0 devices in Verilog and VHDL. It is applicable to the examples for Wires, Triggers, Pipes, and Registers. This boilerplate is familiar if you’ve looked through our samples. To keep the examples brief, we won’t duplicate this code for each one.

module Framework(
          input wire [4:0] okUH,
          output wire[2:0] okHU,
          inout wire[31:0] okUHU,
          inout wire okAA,
          input wire sys_clkn,
          input wire sys_clkp,
          input wire reset
          // Your signals here
     );

     // Clock
     wire sys_clk;

     IBUFGDS osc_clk(
          .O(sys_clk),
          .I(sys_clkp),
          .IB(sys_clkn)
     );

     //FP wires	
     wire okClk;
     wire [112:0] okHE;
     wire [64:0] okEH;
     wire [5*65-1:0] okEHx;
     // Adjust size of okEHx to fit the number of outgoing endpoints in your design (n*65-1:0)

     //Your HDL here

     okHost hostIF (
          .okUH(okUH),
          .okHU(okHU),
          .okUHU(okUHU),
          .okClk(okClk),
          .okAA(okAA),
          .okHE(okHE),
          .okEH(okEH)
     );

     // Adjust N to fit the number of outgoing endpoints in your design (.N(n))
     okWireOR # (.N(1)) wireOR (okEH, okEHx);
     
     // Your FrontPanel module instantiations here

endmodule
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_unsigned.all;

Library UNISIM;
use UNISIM.vcomponents.all;

use work.FRONTPANEL.all;


entity Framework is
     port(
          okUH : in STD_LOGIC_VECTOR(4 downto 0);
          okHU : out STD_LOGIC_VECTOR(2 downto 0);
          okUHU : inout STD_LOGIC_VECTOR(31 downto 0);
          okAA : inout  STD_LOGIC;

          sys_clkp : in STD_LOGIC;
          sys_clkn : in STD_LOGIC;

          -- Your signals here
     );
end Framework;

architecture Behavioral of Framework is
     --FP signals
     signal okClk : STD_LOGIC;
     signal okHE : STD_LOGIC_VECTOR(112 downto 0);
     signal okEH : STD_LOGIC_VECTOR(64 downto 0);
     signal okEHx : STD_LOGIC_VECTOR(65*5-1 downto 0);
     -- Adjust size of okEHx to fit the number of outgoing endpoints in your design (65*n-1 downto 0)
     signal sys_clk : STD_LOGIC;

     --Your signals here

begin

--Your HDL here

osc_clk : IBUFGDS port map (
     O=>sys_clk,
     I=>sys_clkp,
     IB=>sys_clkn
);

-- Instantiate the okHost and connect endpoints
okHI : okHost port map (
     okUH=>okUH, 
     okHU=>okHU, 
     okUHU=>okUHU, 
     okAA=>okAA,
     okClk=>okClk, 
     okHE=>okHE, 
     okEH=>okEH
);

-- Adjust N to fit the number of outgoing endpoints in your design (N=>n)
okWO : okWireOR generic map (N=>5) port map (okEH=>okEH, okEHx=>okEHx);

-- Your FrontPanel Module instantiations here

end Behavioral;