FrontPanel SDK Examples

These pages include a number of resources to help make you more productive with our products. Please refer to the following resources if you need a hand.

Signal State Machine Completion

Detecting state machine completion is best done with Trigger Outs. Like okTriggerIn, okTriggerOut’s ep_trigger should be set synchronously with okTriggerOut’s clock or it might not be captured properly by the okTriggerOut module. Once the trigger out value is set, it will remain set until it is checked and cleared by the PC. To do this on the PC, use the UpdateTriggerOuts() method.

When initializing a state machine, it is recommended but not required that you define a reset signal. In this example, the reset is attached to a trigger, but it can also be attached to a wire.

The pauses in the example are included to make the LEDs readable and are not required for the triggers to operate properly.

When setting TriggerOuts in HDL, it is recommended that you reset the signal to 0 every clock cycle and set it only when the state changes. This ensures that the signal is set for only one clock cycle and thus functions properly as a trigger. If the signal is accidentally set for more than one clock cycle, there is a chance that the PC will read it and it will be set again, resulting in duplicate state notifications.

Note: This section contains both software and HDL portions. The software and HDL must work in tandem if FrontPanel is to be used on the PC end to perform tasks on the FPGA. The HDL in this section is designed to be set within the FrontPanel Framework HDL, available on the HDL Framework page for USB 2.0 and USB 3.0. For specific information about each of these methods or modules, consult the FrontPanel User’s Manual, the FrontPanel API guide, and the samples and README files provided with the FrontPanel download.

okCFrontPanel dev;
dev.OpenBySerial();
dev.ConfigureFPGA("example.bit");

while (1){
     // Trigger state machine
     dev.ActivateTriggerIn(0x40, 0x01);
     std::this_thread::sleep_for(std::chrono::seconds(1));

     // Check for state change
     dev.UpdateTriggerOuts();
     if (dev.IsTriggered(0x60, 0x01) == true){
          std::cout << "In state 1.\n";
     }
     else if (dev.IsTriggered(0x60, 0x10) == true){
          std::cout << "In state 2.\n";
     }
}
okCFrontPanel dev = new okCFrontPanel();
okCFrontPanel.ErrorCode error = new okCFrontPanel.ErrorCode();

dev.OpenBySerial("");
error = dev.ConfigureFPGA("example.bit");
while (true)
{
     // Trigger state machine
     dev.ActivateTriggerIn(0x40, 0x01);
     Thread.Sleep(1000);

     // Check for state change
     dev.UpdateTriggerOuts();
     if (dev.IsTriggered(0x60, 0x01) == true)
     {
          Console.WriteLine("In state 1.");
     }
     else if (dev.IsTriggered(0x60, 0x02) == true)
     {
          Console.WriteLine("In state 2.");
     }
}
dev = ok.okCFrontPanel()
dev.OpenBySerial("")
dev.ConfigureFPGA("example.bit")

while 1 == 1:
     # Trigger state machine
     dev.ActivateTriggerIn(0x40, 0x01)
     time.sleep(1)

     # Check for state change
     dev.UpdateTriggerOuts()
     if dev.IsTriggered(0x60, 0x01) == True:
          print "In state 1."
     elif dev.IsTriggered(0x60, 0x10) == True:
          print "In state 2."
public class example{
     okCFrontPanel dev;
     okCFrontPanel.ErrorCode error;
     Thread t;

     public void Initialize(){
          t = new Thread();
          dev = new okCFrontPanel()
          dev.OpenBySerial("");
          error = dev.ConfigureFPGA("example.bit");
          // It’s a good idea to check for errors here!
     }

     public void Check(){
          // Trigger state machine
          dev.ActivateTriggerIn(0x40, 0x01);
          try{ Thread.sleep(1000); }
          catch(Exception e){ System.out.println(e); }

          // Check for state change
          dev.UpdateTriggerOuts();
          if(dev.IsTriggered(0x60, 0x01) == true){
               System.out.println("In state 1.");
          } else if(dev.IsTriggered(0x60, 0x02){
               System.out.println("In state 2.");
          }
     }
}
// Wire declarations
wire [15:0] start;
wire [15:0] treset;
reg  [15:0] tout;

// Circuit behavior	
integer state;
parameter 
     s_idle = 2'b00,
     s_state1 = 2'b01,
     s_state2 = 2'b10;
	
//next state logic
always @ (posedge clk1)begin
     tout <= 8'h00;
     case(state)
          s_idle: begin
               if (start) begin
                    state = s_state1;
                    led <=8'hAA;
               end
          end
          s_state1: begin 
               if (start) begin
                    state = s_state2;
                    led <= 8'h55;
                    tout <= 8'h01;
               end else begin
                    state = s_state1;
                    led <= 8'hAA;
               end
          end
          s_state2: begin
               if (start) begin
                    state = s_state1;
                    led <= 8'hAA;
                    tout <= 8'h10;
               end else	begin
                    state = s_state2;
                    led <= 8'h55;
               end
          end
          default: begin
               state = s_idle;
               led <= 8'h00;
          end
     endcase
end

// FrontPanel endpoint instantiation
okTriggerIn smstart(
     .ok1(ok1),
     .ep_addr(8'h40),
     .ep_clk(clk1),
     .ep_trigger(start)
);

okTriggerIn smreset(
     .ok1(ok1),
     .ep_addr(8'h42),
     .ep_clk(clk1),
     .ep_trigger(treset)
);

okTriggerOut smout(
     .ok1(ok1),
     .ok2(ok2),
     .ep_addr(8'h60),
     .ep_clk(clk1),
     .ep_trigger({tout})
);
--Circuit signals
signal count : STD_LOGIC_VECTOR(7 downto 0);
signal start_vector : STD_LOGIC_VECTOR(15 downto 0);
signal t_out : STD_LOGIC_VECTOR(15 downto 0) := x"0000";
signal start	 : STD_LOGIC;
signal t_reset : STD_LOGIC;
	
--States
signal state : STD_LOGIC_VECTOR(7 downto 0) := x"01";
constant s_idle : STD_LOGIC_VECTOR(7 downto 0) := x"01";
constant s_state1 : STD_LOGIC_VECTOR(7 downto 0) := x"02";
constant s_state2 : STD_LOGIC_VECTOR(7 downto 0) := x"03";

-- Circuit behavior
start <= start_vector(1);
t_reset <= start_vector(4);

process(clk1, t_reset) begin
     if (t_reset = '1') then
          state <= s_idle;
          led <= x"00";
     end if;
     if rising_edge(clk1) then
          t_out <= x"0000";
          case(state) is
               when s_idle => 
                    if(start = '1') then
                         state <= s_state1;
                         led <= x"AA";
                         t_out <= x"0001";
                    else
                         state <= s_idle;
                         led <= x"00";
                         t_out <= x"0000";
                    end if;
               when s_state1 =>
                    if(start = '1') then
                         state <= s_state2;
                         led <= x"55";
                         t_out <= x"0010";
                    elsif(t_reset = '1') then
                         state <= s_idle;
                         led <= x"00";
                         t_out <= x"0000";
                    else
                         state <= s_state1;
                         led <= x"AA";
                         end if;
               when s_state2 =>
                    if(start = '1') then
                         state <= s_state1;
                         led <= x"AA";
                         t_out <= x"0001";
                    elsif(t_reset = '1') then
                         state <= s_idle;
                         led <= x"00";
                         t_out <= x"0000";
                    else
                         state <= s_state2;
                         led <= x"55";
                    end if;
               when others =>
                    state <= state;
          end case;
     end if;
end process;

-- FrontPanel endpoint instantiation
tcount : okTriggerIn
     port map(
          ok1=>ok1,
          ep_addr=>x"40",
          ep_clk=>clk1,
          ep_trigger=>start_vector
     );

tevent : okTriggerOut
     port map(
          ok1=>ok1,
          ok2=>ok2s( 1*17-1 downto 0*17),
          ep_addr=>x"60",
          ep_clk=>clk1,
          ep_trigger=>t_out
     );