FrontPanel SDK Examples

These pages include a number of resources to help make you more productive with our products. Please refer to the following resources if you need a hand.

Transferring Data

The following example uses a simple FIFO to hold a piped-in value until it is read by the pipe out. Note that the FIFO in this example is two bytes wide, which is the transfer size for a USB 2.0 device. In a USB 3.0 device, a pipe transfer consists of four bytes and should be handled with a four byte-wide FIFO.

In this example, the length of data is being ignored. It is assumed here that the HDL extracts data from the FIFO as available and has no expectation on transfer length.

Note: This section contains both software and HDL portions. The software and HDL must work in tandem if FrontPanel is to be used on the PC end to perform tasks on the FPGA. The HDL in this section is designed to be set within the FrontPanel Framework HDL, available on the HDL Framework page for USB 2.0 and USB 3.0. For specific information about the FrontPanel methods or modules, consult the FrontPanel User’s Manual, the FrontPanel API guide, and the samples and README files provided with the FrontPanel download.

okCFrontPanel dev;
okCFrontPanel::ErrorCode error;
unsigned char dataout[128];
unsigned char datain[128];
int i;
long written;

dev.OpenBySerial();
error = dev.ConfigureFPGA("example.bit");
// It’s a good idea to check for errors here!

// Send brief reset signal to initialize the FIFO.
dev.SetWireInValue(0x10, 0xff, 0x01);
dev.UpdateWireIns();
dev.SetWireInValue(0x10, 0x00, 0x01);
dev.UpdateWireIns();

for (i = 0; i < sizeof(dataout); i++) {
     // Load outgoing data buffer.
}

// Send buffer to PipeIn endpoint with address 0x80
written = dev.WriteToPipeIn(0x80, sizeof(dataout), dataout);
// Read to buffer from PipeOut endpoint with address 0xA0
written = dev.ReadFromPipeOut(0xA0, sizeof(datain), datain);
okCFrontPanel dev = new okCFrontPanel();
okCFrontPanel.ErrorCode error = new okCFrontPanel.ErrorCode();
int n = 128;
byte[] dataout = new byte[n];
byte[] datain = new byte[n];
int i;
byte c;
long written;

dev.OpenBySerial("");

error = dev.ConfigureFPGA("example.bit");
// It’s a good idea to check for errors here!

 // Send brief reset signal to initialize the FIFO.
 dev.SetWireInValue(0x10, 0xff, 0x01);
 dev.UpdateWireIns();
 dev.SetWireInValue(0x10, 0x00, 0x01);
 dev.UpdateWireIns();

 for (i = 0; i < (n * sizeof(byte)); i++)
 {
     // Load outgoing data buffer
 }

// Send buffer to PipeIn endpoint with address 0x80
written = dev.WriteToPipeIn(0x80, n* sizeof(byte), dataout);
// Read to buffer from PipeOut endpoint with address 0xA0
written = dev.ReadFromPipeOut(0xA0, n * sizeof(byte), datain);
dev = ok.okCFrontPanel()

# data buffer in Python (mutable type bytearray) must be initialized upon declaration
dataout = bytearray('abcdefghijklmnopqrstuvwxyz')
datain = bytearray('00000000000000000000000000')

dev.OpenBySerial("")
error = dev.ConfigureFPGA("example.bit")
# It’s a good idea to check for errors here!!

# Send brief reset signal to initialize the FIFO.
dev.SetWireInValue(0x10, 0xff, 0x01);
dev.UpdateWireIns();
dev.SetWireInValue(0x10, 0x00, 0x01);
dev.UpdateWireIns();

# Send buffer to PipeIn endpoint with address 0x80
data = dev.WriteToPipeIn(0x80, dataout)
# Read to buffer from PipeOut endpoint with address 0xA0
data = dev.ReadFromPipeOut(0xA0, datain)
public class example{
     okCFrontPanel dev;
     okCFrontPanel.ErrorCode error;
     byte[] dataout;
     byte[] datain;
     long written;
     int i;
     int n = 128;

     public void Pipes(){
          dev = new okCFrontPanel();
          dev.OpenBySerial("");
          error = dev.ConfigureFPGA("example.bit");
          // It’s a good idea to check for errors here!!

          dataout = new byte[n];
          for(i = 0; i < dataout.length; i++){
               dataout[i] = (byte)i;
          }

          // Send brief reset signal to initialize the FIFO.
          dev.SetWireInValue(0x10, 0xff, 0x01);
          dev.UpdateWireIns();
          dev.SetWireInValue(0x10, 0x00, 0x01);
          dev.UpdateWireIns();

          // Send buffer to PipeIn endpoint with address 0x80
          written = dev.WriteToPipeIn(0x80, dataout.length, dataout);

          // Read to buffer from PipeOut endpoint with address 0xA0
          datain = new byte[dataout.length];
          written = dev.ReadFromPipeOut(0xA0, datain.length, datain);
     }
}
// Circuit wires
wire fifowrite;
wire fiforead;
wire [15:0] datain;
wire [15:0] dataout;
wire reset;
wire [15:0] wireout;
	
//Circuit behavior
assign reset = wireout[0];

// Xilinx Core IP Generated FIFO	
FIFO_16bit fifo(
     .din(datain),
     .dout(dataout),
     .wr_en(fifowrite),
     .rd_en(fiforead),
     .clk(ti_clk),
     .rst(reset)
);
	
// FrontPanel module instantiations
okWireIn wire10(
     .ok1(ok1),
     .ep_addr(8'h10),
     .ep_dataout(wireout)
);

okPipeIn pipe80(
     ok1(ok1),
     .ok2(ok2x[0*17 +: 17]),
     .ep_addr(8'h80),
     .ep_write(fifowrite),
     .ep_dataout(datain)
);

okPipeOut pipeA0(
     .ok1(ok1),
     .ok2(ok2x[1*17 +: 17]),
     .ep_addr(8'hA0),
     .ep_read(fiforead),
     .ep_datain(dataout)
);
--Circuit signals
signal fifowrite : STD_LOGIC;
signal fiforead : STD_LOGIC;
signal datain : STD_LOGIC_VECTOR(15 downto 0);
signal dataout : STD_LOGIC_VECTOR(15 downto 0);
signal reset : STD_LOGIC;
signal wireout	 : STD_LOGIC_VECTOR(15 downto 0);
signal fifofull : STD_LOGIC;
signal fifoem : STD_LOGIC;

-- Component definition goes in architecture portion of VHDL body
COMPONENT FIFO_16bit
     PORT (
          clk : IN STD_LOGIC;
          rst : IN STD_LOGIC;
          din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
          wr_en : IN STD_LOGIC;
          rd_en : IN STD_LOGIC;
          dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
          full : OUT STD_LOGIC;
          empty : OUT STD_LOGIC
     );
END COMPONENT;

-- Circuit behavior

reset <= wireout(0);

--Instantiate FIFO Xilinx Core IP here

fifo : FIFO_16bit
     PORT MAP (
          clk => ti_clk,
          rst => reset,
          din => datain,
          wr_en => fifowrite,
          rd_en => fiforead,
          dout => dataout,
          full => fifofull,
          empty => fifoem
     );

--End FIFO instantiation

-- FrontPanel endpoint instantiation
wire10 : okWireIn 
     port map(
          ok1=>ok1,
          ep_addr=>x"10",
          ep_dataout=>wireout
     );

pipe80 : okPipeIn
     port map(
          ok1=>ok1,
          ok2=>ok2s(1*17-1 downto 0*17),
          ep_addr=>x"80",
          ep_write=>fifowrite,
          ep_dataout=>datain
     );

pipeA0 : okPipeOut
     port map(
          ok1=>ok1,
          ok2=>ok2s(2*17-1 downto 1*17),
          ep_addr=>x"A0",
          ep_read=>fiforead,
          ep_datain=>dataout
     );