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Memory Module for XEM3001 (DRAM and SRAM)
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The RAM3001 memory module provides additional, high-speed memory to the XEM3001 for a variety of purposes including added buffering and low-latency storage.

The SDRAM uses only one of the two 50-pin headers on the XEM3001 leaving the other 50-pin header and 20-pin header for general use. The SyncSRAM uses the opposing 50-pin header as well as the 20-pin header.

Auxiliary Power

Since many applications require power consumption exceeding the 500-mA limit of the USB, the RAM3001 can provide its own 1-A power source. This power source can also be disconnected if your design supplies power or if you choose to use the XEM3001 to supply power.


A 32MByte SDRAM (arranged as 16M x 16-bit words in 4 banks) provides large dynamic storage for memory-hungry applications. With supported clock frequencies to 133 MHz and a 16-bit wide data bus, the SDRAM can handle plenty of memory bandwidth. Opal Kelly provides a sample memory controller to get you started. Other memory controllers are available directly from Xilinx.

256kByte Synchronous SRAM

For applications requiring fast memory bandwidth with low latency and simple memory controllers, 4Mbit pipelined SRAM (arranged as 256k x 16-bitwords) provides unlimited back-to-back read/write operations at up to 133 MHz without wait states.

Physical Design

The RAM3001 has been designed to perfectly stack above or below the XEM3001 depending on your design needs.

Block diagram

Block diagram

Technical Specifications and Support

Features & Specifications

  • Same footprint as the XEM3001 (3.5" x 2.0" / 88.9mm x 50.8mm)
  • 3.3v @ 1A voltage regulator
  • 32 MB Synchronous DRAM (16M x 16) (options -D and -DS)
  • 256 kB Synchronous SRAM (128k x 16) (options -S and -DS)
  • DRAM uses JP2 exclusively
  • SRAM uses JP1 and JP3

Important Note: Firmware source code is not included with the XEM6001.  Of course, full documentation on designing the XEM6001 into your application is included.  Please see the Library items on this page.