Siemens EDA is headquartered in beautiful Wilsonville, OR, near the HQ office of Opal Kelly. Over the decades, Mentor Graphics had become one of Oregon’s largest software leaders focused on electronic design automation (EDA). Mentor was acquired by Siemens in 2017 and became Siemens EDA. Siemens EDA provides design solutions that enable companies to develop better electronic products faster and more cost-effectively.
As a leading software supplier, Siemens looks to trusted partners when it needs a hardware component to complete its solutions. This is the case with Siemens’ Tessent SiliconInsight solution, a benchtop mini-tester for the silicon validation and debug phase. Software alone was not enough. Integrating Opal Kelly FPGA modules and FrontPanel SDK, with their software simulation tools, Siemens delivers a very powerful mini-tester that is able to handle the most difficult and I/O intensive cases.
A Global Race for ASIC Development Slowed by Testing Bottlenecks
There is a global race to develop massive new “powerhouse” ASICs. Siemens’ customers are these developers – visionary IC manufacturers developing complex chips for automotive, 5G, networking, and AI applications. The race is all about time-to-market and the prize may well go to the companies that eliminate the bottlenecks that prevent them from getting their chips to market first.
“Reducing the time spent on silicon bring-up is critical in getting ICs into the hands of customers and staying competitive. Typically, the silicon bring-up process involves converting the test patterns to a tester-specific format and generating a test program that is executed by Automatic Test Equipment (ATE). This standard silicon bring-up flow is becoming too slow and expensive, especially for very large designs with complex DFT [design for test] structures,” said Matthew Knowles, Operations Product Management, Silicon Yield and Bring-Up, Siemens.
Third-party ATE rental expenses and limited availability are just the tip of the iceberg when it comes to the pain associated with the traditional approach to chip test and debug. There is also a significant impact on team productivity and product quality.
Additional disadvantages of the traditional ATE workflow include:
- Expensive – Beyond ATE rental costs, there are upfront costs of test program development, and load-board development.
- Time consuming – Time between arrival of first silicon at the test house and shipping validated parts is long:
- Development moves from a stream-lined parallel development process to a serial testing process
- Complexity of ATE activities when coordinating with the third party ATE group
- Communication overhead until all tests are running smoothly and correctly
- Error prone: The back-and-forth between engineers and the third party ATE group can be error prone with confusion and delays – language differences, time zone differences, shipping delays, etc.
Software is Not Enough; Hardware Required
While able to build the software solution to meet this race, to serve its most challenging customers, Siemens needed a capable hardware partner. Siemens required not only a proven and reliable off-the-shelf adaptor board, but also a software interface to that board, to integrate with the Siemens software, to create a seamless user experience.
The Solution: Hardware from Opal Kelly
Siemens analyzed the bottlenecks in the design process, and developed a remarkable solution – the combination of their desktop ATE software partnered with Opal Kelly’s off-the-shelf FPGA modules.
“The SiliconInsight desktop solution provides 10 times time-to-market advantage with the Opal Kelly XEM6310,” Knowles commented.
In addition to providing the most I/O of the approved adaptor boards, Siemens has integrated the Opal Kelly FrontPanel SDK into the Siemens solution with built-in gateware. This gateware enables control of the Opal Kelly FPGA module through the SiliconInsight software, enabling users to recognize and work with the Opal Kelly module directly through their Siemens solution. While other adaptor boards are offered, Siemens recommends Opal Kelly for their customers that need the most I/O and control.
Opal Kelly’s FrontPanel SDK is an easy-to-use, robust API for communication, configuration, and interfacing to PC, Mac or Linux hardware. FrontPanel handles all the interaction between the software and the FPGA internals, dramatically reducing the time and effort required to interface to a design.
Siemens used the FrontPanel SDK to integrate the Opal Kelly FPGA module into their solution. They built gateware around FrontPanel HDL to build a flexible and capable hardware adaptor to communicate with customer ASICs. Then they integrated the FrontPanel API into their desktop ATE software to create a seamless link between the simulation tools and the hardware ASIC.
The Siemens/Opal Kelly solution solves many of the key problems of ATE-based silicon bring up and delivers significant benefits over the traditional approach:
- Convenient: Enables real-time testing at the desktop.
- Easier: Streamlines communications between the distributed teams. Apples-to-apples — multiple desktop/benchtop units can have a common test environment.
- Cost Savings: Order of magnitude less expensive by eliminating the cost of using a third party ATE.
- Faster: Eliminates the need reserving time on time-restricted ATE, and the back-and-forth of set up and run.
“As next-generation chip development has become more complicated, and as development times have accelerated in the highly-competitive category, Siemens has developed tools with intelligent ‘self-test’ built into the chips,” Knowles said. “This is an order of magnitude cheaper device and gives engineers a tool they couldn’t afford to buy. They can test everything now, without spending thousands and thousands of dollars.”
Siemens and its customers, with the assistance of Opal Kelly modules, are developing Design for Test (DFT) implementations to test massive chip designs. This approach minimizes test costs and enables quick silicon bring-up for the fastest shipping of the first parts.
“By adding the Opal Kelly adaptor board, Siemens’ customers are able to perform ATPG debug and diagnosis. This is the logic scan part of the device testing which is becoming more and more complex. This drives the need for more debug, characterization and diagnosis of issues encountered during the first silicon bringup and small batch testing,” Knowles said.
Two Opal Kelly modules have been selected for use with Tessent SiliconInsight, the XEM6310 and XEM8350. These Opal Kelly FPGA modules serve as “translators” from computer, through USB, to chip as the Opal Kelly module scans the patterns for the structural self-test.
Opal Kelly modules provide the mixture of key capabilities required:
- High-speed interface
- Memory configuration
- Software support
The XEM6310 is a USB 3.0 integration module based on the Xilinx Spartan-6 FPGA. The SuperSpeed USB interface provides FPGA gateway configuration and data transfer at up to 350 MB/s.
Until recently, the XEM6310 had been the most I/O-rich adaptor board offered by Siemens, accessing 120 device pins. Need more I/O? The XEM8350 provides an I/O-rich solution for Siemens’ customers to expand features / capabilities without having to re-engineer software.
The XEM8350 is a high-performance integration module based on the Xilinx Kintex UltraScale FPGA. In addition to a high gate-count FPGA, equipped with over 330 I/O and 28 high-speed transceiver lanes to communicate with numerous sensor devices and networks, the XEM8350 also has two independent USB 3.0 interfaces to transfer data in and out of a host computer for storage or deeper processing. The XEM8350 employs two fully-independent SuperSpeed USB 3.0 interfaces for configuration downloads and data transfer. With integrated DDR4, power supplies, platform flash, high-speed transceivers, Samtec mezzanine connectors, and voltage/current/temperature monitoring, the XEM8350 is ideal for ultra high-end data acquisition and computation loads.
“The combination of Tessent SiliconInsight and the Opal Kelly FPGA module provides a low-cost, desk-top testing configuration tool for automatic test pattern generation at 1/10 the price of a traditional ATE rental. They can test everything mow, without spending thousands of dollars,” Knowles said.
Case Study within a Case Study
Graphcore, a Siemens/Opal Kelly mutual customer, works in the highly competitive field of hardware accelerated Artificial Intelligence (AI). They need to get their products to market quickly for a competitive edge. Their bottleneck? Securing and paying for time on the rented ATE testing equipment.
Instead, Graphcore created a test solution in-house, not based on expensive ATE, but instead centered on Siemens’ SiliconInsight product, with Opal Kelly XEM6310 adaptor board. Tessent SiliconInsight forms part of a larger test executive written in TCL and handles all of the device structural testing. This software, running on a standard Linux PC, sends and receives data to/from a breakout board through an USB 3.0 connector. The breakout board parallelizes the serial data to a maximum of 120 data pins, which in turn are connected to the AI chip evaluation board.
The results: High quality, cost effective test with fast turn-around time and reduced DFT effort.
Graphcore’s fully automated Siemens/Opal Kelly/in-house solution has dramatically accelerated time-to-market for its new AI device – the most complicated, highest transistor-count IC ever built (at the time it was launched). Silicon bring-up of 23 billion transistors took just three days.
“With this software and hardware solution we can bring-up the device and all test patterns within a day, without sacrificing any test quality. The combination of a full Siemens DFT flow and custom automation allowed us to ship tested and validated first silicon parts within a week,” said Phil Horsfield, vice president of Silicon at Graphcore
“Graphcore developed a test strategy – for its 24 billion transistor AI chip – that achieved silicon bring-up and prototype ship in less than three days, instead of weeks,” Knowles said.
“Tessent SiliconInsight achieves the same quality results as traditional tester-based diagnosis methods with a significantly shorter root cause cycle time. Enabling an easy and cost-effective way to execute and validate ATPG patterns on silicon when first samples arrive.”
The combined solution:
- Reduces silicon bring-up costs, including saving money on ATE rentals
- Improves productivity: Replicating in-house test setups for globally dispersed teams, insures like-to-like comparisons, reduces confusion and improves collaboration
- Accelerates “time to answers”
- Keeps control of product development in house
- Accelerates time-to-market
Reducing the time and expense of silicon bring-up lends a competitive advantage to any IC company. The traditional silicon bring-up, debug, and characterization process is prone to errors and unpredictable schedules and expenses, and does not keep up with the accelerated approach to product development. Siemens and Opal Kelly together provide a better, less expensive way.
“The Tessent SiliconInsight and Opal Kelly solution is an order of magnitude, or two, cheaper than renting and expensive ATE. Now, every engineer can have one or two of these desktop testers and they can test everything, without having to spend and wait,” Knowles concluded.