Introducing Pins – Interactive Online Reference
We’re very excited to introduce you to Pins our new interactive online reference for Opal Kelly integration module pinouts.
Traditionally, our module pin lists (the list of all expansion connector pins, their functional description, and the FPGA pin location they are mapped to) have been documented in a static table in our PDF documentation. This table is easy to read, but can become unwieldy for modules with lots of pins, manually copying entries from the table is error prone, and the amount of information we can capture for each pin is somewhat limited by the presentation. Below is an example from our XEM6310MT User’s Manual.
Luckily all of these limitations are a thing of the past thanks to Pins. Pins is our new online reference for pin lists. Each of our products now has its own Pin List on our website where you can browse, filter, and search interactively to become familiar with the device’s expansion connectors. View Pins for pin lists of our existing products below and read on for more information.
Pins represents a number of common signal, pin, and PCB characteristics as symbols to make pin lists easier to read, faster for visual scanning, and more reliable for reference. For example, here’s a view of the pin list for our recently-announced XEM6310MT.
With the improved presentation allowed by Pins, we’re able to put a lot more information into our pin lists for enhanced reference. Depending on the task and application, this additional information might be a bit overwhelming. Simply disable table columns that you don’t need or put visible columns in any order you like. When you need them back, they’re only a click away.
We’ve populated each pin list with a number of additional attributes to help you sort through them. By defining filters, Pins displays only the pins that match your criteria, giving you a concise view of exactly the device connections that you’re looking for.
With live search, you can quickly and easily find signals, attributes, functions, pin locations, or basically anything you’re looking for in the pin list. Three search modes allow you to highlight, hide, or show only those pins that match your search text.
Peripherals and Constraint File Generation
The real coup de grâce of Pins over static pin list tables is the Peripherals feature. With a Pins account, you can add information about your FPGA design to a pin list. Enter design signal net names on each pin and additional constraint information such as I/O standard and drive strength. Pins saves this information as a Peripheral. Create as many as you like and even share them publicly or privately. Pins will automatically generate your Xilinx UCF or Altera QSF constraint file for you with the information you’ve entered.
You can read more about Pins and sign up for an account at www.opalkelly.com/pins.