FrontPanel Tutorial (archived)

Note: This tutorial is outdated and no longer maintained to be consistent with the latest FrontPanel SDK or Xilinx tools. Please review the FrontPanel User’s Manual for the latest information and use the current Samples (and their README) from your installation as guidance.

Introduction

This tutorial will walk you through the process of creating a new design project on the XEM3001. It is intended as an introduction to using the Xilinx Project Navigator (part of the ISE WebPack) with the XEM3001. In order to start the tutorial, you will need to have the ISE WebPack installed on your computer. You can download the WebPack for free at Xilinx’s website: http://www.xilinx.com.

Note: This tutorial is not intended to be a tutorial on FPGA design or a tutorial on using Xilinx’s ISE software. Rather, this tutorial is written to help you quickly target the XEM3001, use the FrontPanel software, and construct interfaces between the PC and FPGA. Xilinx has several useful guides and documents describing the ISE package.

Organization

This tutorial is divided into three parts:

Part I

Start Part I: The first part guides you through creating a new design with Xilinx’s Project Navigator (a simple counter) and downloading that design to the XEM3001 using FrontPanel. The design in this part uses no FPGA/PC communication other than downloading the configuration file.

Requirements:

• Xilinx ISE WebPack (version 8.1i or later)
• Opal Kelly FrontPanel

Part II – FPGA/PC Communication

Start Part II: The second part is based on the First sample included on the CD shipped with your XEM. The input and output are provided through FrontPanel HDL components on the FPGA and FrontPanel GUIcomponents on the PC.

Requirements:

• Xilinx ISE WebPack (version 8.1i or later)
• Opal Kelly FrontPanel

Part III – Software API

Start Part III: This part uses an implementation of a DES core from OpenCores.org. Here we add to the DES implementation so that an entire block of data can be encrypted or decrypted. The block is transferred to and from the FPGA using the FrontPanel C++ API. A simple console application is provided as the PC-side interface to the hardware design.

Requirements:

• Xilinx ISE WebPack (version 8.1i or later)
• Opal Kelly FrontPanel
• Visual Studio .NET (7.0 or 7.1)

Part IV – Simulation

Start Part IV: In this section we work through a complete simulation of the DES tester, including full simulation of the PC/FPGA interaction.

Requirements:

• ModelSim XE III (6.0a or later)
• Opal Kelly FrontPanel