FrontPanel Tutorial – Part 2 (archived)

Note: This tutorial is outdated and no longer maintained to be consistent with the latest FrontPanel SDK or Xilinx tools. Please review the FrontPanel User’s Manual for the latest information and use the current Samples (and their README) from your installation as guidance.

Part II – Adding PC Connectivity Using FrontPanel HDL and XML

Approximate time to complete this part: 30 minutes

This part of the tutorial introduces the PC/FPGA connectivity provided by the FrontPanel HDL modules, the USB firmware loaded on the XEM3001, and the FrontPanel application. It is based on the First sample included with your XEM. The sample source files may be found in the Samples folder in your installation directory.

Setup the FPGA Project

Setup a new HDL project within Project Navigator as you did in the first part of this tutorial. You can name the toplevel HDL file first.v.

Now, we need to add the files necessary to implement FrontPanel capability in the FPGA design. These include a Verilog or VHDL file (okLibrary.v) and several pre-synthesized modules (*.ngc). The HDL file needs to be added to the project. The pre-synthesized modules can simply be placed in the project directory; the Xilinx tools will find and use them during the appropriate steps during build.

  • okLibrary.v
  • okHostInterfaceCore.ngc
  • okWireIn.ngc
  • okWireOut.ngc

Once the project is setup correctly, the source panel in Project Navigator will look something like the one shown below.

Create the Toplevel HDL

Our toplevel HDL needs to include the following hardware descriptions:

  • Instantiated FrontPanel Host Interface
  • Instantiated FrontPanel HDL modules for USB communication
  • User logic

The first two items are done using cookbook HDL which will be similar among all FrontPanel HDL projects. Shown below is a code snippet. For the First sample, we have three inputs and two outputs. The inputs and outputs are all 16-bit data values.

okHostInterface okHI(.hi_in(hi_in), .hi_out(hi_out), .hi_inout(hi_inout),
		.ti_clk(ti_clk), .ok1(ok1), .ok2(ok2));
okWireIn ep00 (.ok1(ok1), .ok2(ok2), .ep_addr(8'h00), .ep_dataout(ep00wire));
okWireIn ep01 (.ok1(ok1), .ok2(ok2), .ep_addr(8'h01), .ep_dataout(ep01wire));
okWireIn ep02 (.ok1(ok1), .ok2(ok2), .ep_addr(8'h02), .ep_dataout(ep02wire));
okWireOut ep20 (.ok1(ok1), .ok2(ok2), .ep_addr(8'h20), .ep_datain(ep20wire));
okWireOut ep21 (.ok1(ok1), .ok2(ok2), .ep_addr(8'h21), .ep_datain(ep21wire));

Our user logic is very simple and is shown below. It simply creates an adder and also wires our inputs (from the PC) to the on-board LEDs and the on-board buttons to the outputs (to the PC for display).

assign led      = ~ep00wire[7:0];
assign ep20wire = {12'b0000, ~button};
assign ep21wire = ep01wire + ep02wire;

Add Constraints for the FrontPanel Host Interface

With the addition of the FrontPanel Host Interface, we have several new pins to connect to the FPGA. These pins are routed on the XEM3001 circuit board between the USB microcontroller and the FPGA. These connections are shown below for the XEM3001.

NET "hi_in<0>"		LOC = "P79";
NET "hi_in<1>"		LOC = "P57";
NET "hi_in<2>"		LOC = "P58";
NET "hi_in<3>"		LOC = "P78";
NET "hi_in<4>"		LOC = "P61";
NET "hi_in<5>"		LOC = "P62";
NET "hi_in<6>"		LOC = "P63";
NET "hi_in<7>"		LOC = "P64";
NET "hi_out<0>"		LOC = "P81";
NET "hi_out<1>"		LOC = "P85";
NET "hi_inout<0>"	LOC = "P67";
NET "hi_inout<1>"	LOC = "P68";
NET "hi_inout<2>"	LOC = "P72";
NET "hi_inout<3>"	LOC = "P74";
NET "hi_inout<4>"	LOC = "P86";
NET "hi_inout<5>"	LOC = "P87";
NET "hi_inout<6>"	LOC = "P90";
NET "hi_inout<7>"	LOC = "P92";
NET "hi_inout<8>"	LOC = "P93";
NET "hi_inout<9>"	LOC = "P94";
NET "hi_inout<10>"	LOC = "P95";
NET "hi_inout<11>"	LOC = "P96";
NET "hi_inout<12>"	LOC = "P97";
NET "hi_inout<13>"	LOC = "P100";
NET "hi_inout<14>"	LOC = "P101";
NET "hi_inout<15>"	LOC = "P102";

Building the Interface Using FrontPanel XML Components

Now that our FPGA is designed, we will build a FrontPanel GUI to interface to it via USB. The FrontPanel GUI is composed in XML using tags specific to FrontPanel. These tags define objects such as pushbuttons, trigger buttons, numerical entry, and numerical display items as well as the properties for these items.

Although the XML profiles are relatively simple to write, they can become quite long because each object may take several lines of XML to describe. For brevity, we have only included snippets from the XML for this project. The complete XML is contained in the project.

PLL Configuration: Although it is not necessary, in this project we will include a PLL object so that the PLL onboard the XEM3001 is configured when the profile is loaded. We’ll set the VCO frequency to 400 MHz and the clock output #1 (clk1) to 50 MHz by setting divider #1 to 8.

<object class="okPLL22150">
   <divider1 source="vco">8</divider1>
   <output0 source="div1byn">on</output0>

Adder Inputs: The inputs to this design are two 16-bit numerical values providing. These will be provided by okDigitEntry components which can provide multi-bit numerical entry in binary, octal, hex, or decimal radixes.

<object class="okDigitEntry">
	<tooltip>SUM input A</tooltip>

Adder Output: The output from the adder is a 16-bit word. It will be displayed using the okDigitDisplay component which is a read-only version of the okDigitEntry component.

<object class="okDigitDisplay">
	<tooltip>SUM result</tooltip>

Using the New Design

You may now plugin your XEM3001 and start FrontPanel. Once the configuration bitfile is downloaded to the FPGA, FrontPanel will look as below. Note the colored icon in the right corner of the status bar at the bottom indicating that the FrontPanel host interface was detected and that your design can communicate with FrontPanel.

When you load the XML profile First.xfp into FrontPanel, the GUI panel will pop up displaying the GUI elements we have described in XML. You can now enter inputs to the adder, and watch as the outputs update immediately.

The FrontPanel application window is typically sized to contain just the action buttons at the top. However, if you expand the window, you will see a list of the XML components that have been loaded from the profile as well as some of their properties. This list can be helpful in composing your XML or HDL since it provides a quick reference to the components.

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