Opal Kelly Blog

Pro Tip: Create Memory Interfaces Quickly with Vivado Board Files

AMD-Xilinx’s 7-Series and UltraScale Memory Interface Generators (MIG) are complex gateware and primitive instantiation generators for DDR memory. They can be configured with seemingly endless parameters, and because it implements a physical interface outside the FPGA, your board vendor is the appropriate source for this configuration. It can be a grueling process to manually enter vendor provided configuration settings, and is prone to user error. Additionally, it can be tough for vendors to provide up-to-date configurations for their boards as variations in both Vivado and the MIG’s version can affect the generated output products of the MIG.

With our recent support for Vivado Board Files, instantiating and using memory interfaces in your design just got a lot easier. We maintain MIG configuration parameters within our Board Files for all USB3 boards at AMD-Xilinx’s Board Store for separate Vivado versions v2021.1 and later. AMD-Xilinx’s Board Store repository, and in turn our Board Files, is seamlessly integrated into the Vivado GUI and allows access by the user with no additional step outside installation of the board file. Configuring your project to use our Board Files allows seamless access to our Vivado version’s specific MIG parameter configuration.

Using TCL scripting, users can create a toolbar command to gather our MIG configuration parameters from AMD-Xilinx’s Board Store repository and apply them to an instantiation of the MIG. See “Create Toolbar Command” for more information. An example is shown below:

In the IP Integrator (IPI) Project Mode, the MIG’s configuration parameters are applied automatically when you instantiate the DDR board component:

Vivado Board Files are available for all current-generation Opal Kelly modules including:

Visit our Documentation Portal to learn more about using Vivado Board Files with our products.